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NJU6475B
PRELIMINARY
12-Character 4-Line Dot Matrix Low Power LCD Controller Driver with key Scan Function
GENERAL DESCRIPTION The NJU6475B is a Dot Matrix LCD Controller Driver for 12-character 4-line with Icon display in single chip. It contains voltage converter, voltage regulator, bleeder resistance, CR oscillator, instruction decoder, character generator ROM/RAM, high voltage operation controller/driver and key scan circuit. The voltage converter generates (about 8V) from the supply voltage (3V) and regulated by the regulator. The bias level of LCD driving voltage is generated of high value bleeder resistance and the buffer amplifier matches the impedance. 16-step contrast control function is incorporated for its adjustment. Therefore, simple power supply circuit and easy contrast adjustment are available. The complete CR oscillator is incorporated without external components for oscillation circuit. The microprocessor interface circuit which operates by 1MHz, can be selected serial interface. The character generator ROM consisting of 10,080bits stores 252 kinds of character Font. Each 160bits CG RAM and Icon display RAM can story 4 kinds of special character to display on the dot matrix display area or 128 kinds of Icon on the display area. FEATURES PACKAGE OUTLINE
NJU6475B
*12-Character 4-Line Dot Matrix LCD Controller Driver *Maximum 128-Icon Display *Serial CPU Interface - 48 x 8 Bits :Maximum 12-Character 4-Line Display *Display Data RAM - 10,080 Bits:252 Characters (5 x 8 Dots) *Character Generator ROM - 32 x 5 Bits :4 Patterns (5 x 8 Dots) *Character Generator RAM - 32 x 5 Bits :Maximum 128-Icon *Icon Display RAM : 37-Common/63-Segment *High Voltage LCD Driver : 1/36 duty 1/7Bias *Duty & Bias Ratio : Clear Display, Return Home, Display On/Off Control *Useful Instruction Set *Common and Segment Driver location Order Select Function (Mode-A, Mode-B) *Power On Reset Circuit On Chip *Hardware Reset *Voltage Regulator On Chip *Electrical Variable Resistance On Chip *32-key scan function (8 x 4 Matrix) *Oscillation circuit On Chip *Voltage Converter (Doubler,Tripler) On Chip *Bleeder Resistance On Chip *Low Oprating Current - 2.4V to 3.6V (Except For LCD Driving Voltage) *Operating Voltage - Bumped-Chip / TCP *Package Outline *C-MOS Technology
Display Blink,Cursor Shift, Character Shift
NJU6475B
PAD LOCATION
NJU6475B
PAD COORDINATES Chip Size
PAD No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PAD Mode A ALI-A1 OSC1 OSC2 V5 VSS V5OUT C2C2+ C1C1+ VDD VR VREG TEST SEL
RESET
Name Mode B ALI-A1 OSC1 OSC2 V5 VSS V5OUT C2C2+ C1C1+ VDD VR VREG TEST SEL
RESET
X=(um) -6240 -6020 -5775 -5479 -4979 -4479 -3979 -3479 -2979 -2479 -1979 -1479 - 979 - 531 - 302 - 74 155 383 612 840 1069 1298 1536 1773 2010 2247 2484 2721 2958 3195 3466 3632 3903 4068 4244 4352 4460 4568 4676 4784 4892 5000 5217 5417 5617 5817 6017 6217 6217 6017
Y=(um) -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 1090 1090
P/S RS R/W E/SCL
LCD/KEY
P/S RS R/W E/SCL
LCD/KEY
REQ DB7/CS
DB6/SIO
REQ DB7/CS
DB6/SIO
DB5 DB4 DB3 DB2 DB1 DB0 K0 K1 K2 K3 S0 S1 S2 S3 S4 S5 S6 S7 NC NC NC NC NC ALI-A2 ALI-B2 NC
DB5 DB4 DB3 DB2 DB1 DB0 K0 K1 K2 K3 S0 S1 S2 S3 S4 S5 S6 S7 NC NC NC NC NC ALI-A2 ALI-B2 NC
11.22x2.5mm PAD PAD No. Mode A 51 NC 52 NC 53 NC 54 NC 55 NC 56 NC 57 NC 58 NC 59 NC 60 NC 61 NC 62 NC 63 NC 64 SEGS1 65 COM9 66 COM10 67 COM11 68 COM12 69 COM13 70 COM14 71 COM15 72 COM16 73 COM25 74 COM26 75 COM27 76 COM28 77 COM29 78 COM30 79 COM31 80 COM32 81 SEGM1 82 SEG1 83 SEG2 84 SEG3 85 SEG4 86 SEG5 87 SEG6 88 SEG7 89 SEG8 90 SEG9 91 SEG10 92 SEG11 93 SEG12 94 SEG13 95 SEG14 96 SEG15 97 SEG16 98 SEG17 99 SEG18 100 SEG19
(Chip Center X=0um,Y=0um) Name X=(um) Y=(um) Mode B NC 5817 1090 NC 5617 1090 NC 5417 1090 NC 5217 1090 NC 5017 1090 NC 4817 1090 NC 4617 1090 NC 4417 1090 NC 4217 1090 NC 4017 1090 NC 3817 1090 NC 3617 1090 NC 3417 1090 SEGS1 3160 1090 COM9 2780 1090 COM10 2700 1090 COM11 2620 1090 COM12 2540 1090 COM13 2460 1090 COM14 2380 1090 COM15 2300 1090 COM16 2220 1090 COM25 2140 1090 COM26 2060 1090 COM27 1980 1090 COM28 1900 1090 COM29 1820 1090 COM30 1740 1090 COM31 1660 1090 COM32 1580 1090 SEGM2 1500 1090 SEG60 1420 1090 SEG59 1340 1090 SEG58 1260 1090 SEG57 1180 1090 56 SEG 1100 1090 SEG55 1020 1090 SEG54 940 1090 SEG53 860 1090 SEG52 780 1090 SEG51 700 1090 SEG50 620 1090 SEG49 540 1090 SEG48 460 1090 SEG47 380 1090 SEG46 300 1090 SEG45 220 1090 SEG44 140 1090 SEG43 60 1090 SEG42 - 20 1090
NJU6475B
PAD No.
101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134
PAD Mode A SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53
Name Mode B SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8
X=(um) - 100 - 180 - 260 - 340 - 420 - 500 - 580 - 660 - 740 - 820 - 900 - 980 -1060 -1140 -1220 -1300 -1380 -1460 -1540 -1620 -1700 -1780 -1860 -1940 -2020 -2100 -2180 -2260 -2340 -2420 -2500 -2580 -2660 -2740
Y=(um) 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090
PAD No.
135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 167 168 169
PAD Mode A SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEGM2 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COMM4 COMM3 COMM2 COMM1 COMS1 NC NC NC NC ALI-B2
Name Mode B SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEGM1 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COMM4 COMM3 COMM2 COMM1 COMS1 NC NC NC NC ALI-B2
X=(um) -2820 -2900 -2980 -3060 -3140 -3220 -3300 -3380 -3460 -3540 -3620 -3700 -3780 -3860 -3940 -4020 -4100 -4180 -4260 -4340 -4420 -4500 -4580 -4660 -4740 -4820 -4900 -4980 -5085 -5285 -5485 -5885 -6085 -6240
Y=(um) 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090 1090
NJU6475B
BLOCK DIAGRAM
NJU6475B
TERMINAL DESCRIPTION PAD No. 11,5 4 2,3 Symbol VDD,VSS V5 OSC1, OSC2 I/O I/O Function Power Source : VDD=+3V LCD driving voltage System clock terminal Oscillation C and R are incorporated. (Normally Open) For external clock operation, the clock should be input on OSC1. Serial input select terminal (fixed to "L") Register selection signal input terminal "0" instruction register. (Writing) "1" Data register. (Writing, Reading) Read(R) / Write(W) selection signal input terminal Serial clock input terminal Chip select signal Data input terminal (3-state data bus.) GND : VSS=0V
17
P/S
I
18
RS
I
19 20 23 24 25 - 30 22
R/W E/SCL DB7/CS DB6/SIO DB0 - DB5 REQ
I I I I/O I O
I/O port output terminal This terminal normally output "L". When confirm a key action, REQ terminal output puls. Fix to "H" Level Key scan signal data output terminal Open Drain Output Key scan data input terminal In case of non use, fix to "H". Common signal output terminal
21 35 - 42
LCD/KEY So -S7
I O
31 - 34
K0 - K3
I
158 - 151 65 - 72 150 - 143 73 - 80 162 - 159
COM1 - COM32
O
COMM1 COMM4 COMS1
O
Icon common display signal output terminal
163
O
Static driving common signal output terminal When power down mode VDD or VSS levels are output. Segment signal output terminal Icon segment driving signal output terminal
82 - 141 81,142
SEG1 - SEG60 SEGM1,SEGM2
O O
NJU6475B
PAD No. 57 Symbol SEGS1 I/O O Function Static driving segment signal output terminal When power down mode VDD or VSS level are output. Step up voltage capacitor connecting terminal
10,9 8,7 6 13
C1 C1 C2+,C2V5OUT VREG
+
-
I/O
O O
Step up voltage output terminal Voltage regulator output terminal Connect the resistor between this terminal and VR terminal. Reference voltage for voltage regulator input terminal Connect the resistor between this reference voltage and VDD terminal. Reset terminal When the "L" level input over than 1.2ms to this terminal, the system is reset (at fosc=180KHz). Common and Segment driver location order select terminal. "0" Mode A location (See PAD COORDINATES) "1" Mode B location (See PAD COORDINATES) Maker test terminal This terminal should be connected to VSS (or open.) Non connection terminal
These terminals are electrically open.
12
VR
I
16
RESET
I
15
SEL
I
14
TEST
I
43 - 47 50 - 63 164 - 168 169 49 1 48
NC
-
ALI-A1 ALI-A2 ALI-B1 ALI-B2
-
Alignment mark These terminals are electrically open.
NJU6475B
FUNCTIONAL DESCRIPTION (1) Description for each blocks (1-1) Register The NJU6475B incorporates three 8-bit registers, an instruction register (IR), and a Data Register (DR), Key Register (KR). The register (IR) stores an instruction code such as "clear display" and "cursor shift" or address data for Display Data RAM (DD RAM), Character Generator RAM (CG RAM) and Icon Display RAM (MK RAM). The MPU can write the instruction code and address data to the register (IR), but it cannot read out from register (IR). The Register (DR) is a temporary register, the data stored in the Register (DR) is written into DD RAM, MK RAM. A register from these two registers is selected by the register select signal (RS). Register (KR) is an only temporary register for key scan data. This Register (KR) can read out the contents when selected Key signal at "H" signal. And non relation ship with signal of register select (RS). The Relation ship with RS, R/W register as shown below.

Register selection RS 0 0 1 1 R/W 0 1 0 1 Operation IR write & internal register operation mode (Clear Display etc...) Read out (KR) Write (DR) & internal register operation mode (DR DD RAM/CG RAM/MK RAM) Read out (KR)
(1-2) Address Counter (AC) The address counter (AC) addresses the DD RAM, CG RAM or MK RAM. When the address setting instruction is written into register (IR), the address information is transferred from register (IR) to the address counter (AC). The selection of DD RAM, CG RAM or MK RAM is also determined by this instruction. After writing (or reading) the display data to (or from) the DD RAM, CG RAM or MK RAM, the address counter (AC) increments (or decrements) automatically.
(1-3) Display Data RAM (DD RAM) The display data RAM (DD RAM) consisting of 48 x 8 bits stores up to 48-character display data represented in 8-bit code. The DD RAM address data set in the address counter (AC) is represented in Hexadecimal code.
(Example) DD RAM Address "08" upper order bit AC AC6 AC5 AC4 lower order bit AC3 AC2 AC1 AC0 0 0 0 0 1 0 8 0 0
hexadecimal
hexadecimal
NJU6475B
(1-3-1) The relation between DD RAM address and display position on the LCD
-12-Characters 4-Line Display
1 1st Line 2nd Line 3rd Line 4th Line 00 10 20 30 2 01 11 21 31 3 02 12 22 32 4 03 13 23 33 5 04 14 24 34 6 05 15 25 35 7 06 16 26 36 8 07 17 27 37 9 08 18 28 38 10 09 19 29 39 11 0A 1A 2A 3A 12 0B 1B 2B 3B Display Position DD RAM Address (Hexadecimal)
When the display shift is performed, the DD RAM address changes as follows:
[Left shift display] (00) (10) (20) (30) 01 11 21 31 02 12 22 32 03 13 23 33 04 14 24 34 05 15 25 35 06 16 26 36 07 17 27 37 08 18 28 38 09 19 29 39 0A 1A 2A 3A 0B 1B 2B 3B 00 10 20 30
[Right shift display] 0B 1B 2B 3B 00 10 20 30 01 11 21 31 02 12 22 32 03 13 23 33 04 14 24 34 05 15 25 35 06 16 26 36 07 17 27 37 08 18 28 38 09 19 29 39 0A 1A 2A 3A (0B) (1B) (2B) (3B)
(1-4) Character Generator ROM (CG ROM) The Character Generator ROM (CG ROM) stores 5 x 8 dots character pattern represented in 8-bit character code. The capacity is up to 252 kinds of 5 x 8 dots character pattern. The correspondence between character code and standard character pattern of NJU6475B is shown in table 2. User defined character patterns (Custom Font) are also available by mask option. (in this case, the address (20)H are using for "Space Pattern".)
NJU6475B

The Correspondence Between Character Code and Standard Character Pattern (ROM Version -02)
NJU6475B
(1-5) Character Generator RAM (CG RAM) The Character Generator RAM stores any kinds of character pattern in 5 x 8 dots written by the user program to display user's original character pattern. The CG RAM can store 4 kinds of character in 5 x 8 dots mode. To display user's original character pattern stored in the CG RAM, the address data (00)H -(03)H should be written to the DD RAM as shown in Table-3.

Correspondence of CG RAM address, DD RAM character code
and CG RAM character pattern (5 x 8 dots) Character Code (DD RAM Data) 76543210 Upper Bits Lower Bits Character Pattern (CG RAM Data) 43210 Upper 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 0 Lower 10 01 01 10 00 10 01 00 01 10 11 00 11 00 00 00
CG RAM Address 76543 Upper 210 Lower 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001
00000000
01000
00000001
01001
1 0 0 1 0 0 0 0 0 1 1 0 1 0 0 0
1 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0
Character Pattern Example (1)
Cursor Position Character Pattern Example (2)
Cursor Position
00000011
01011 1 1 1 1 0 0 1 1 0 1 0 1
Notes : 1. Character code bit 0,1 correspond to the CG RAM address bit 3,4 (2bits ; 4patterns). 2. CG RAM address 0 to 2 designate character pattern line position. The 8th line should be "0". If there is "1" in the 8th line, but bit "1" is always displayed on the cursor position regardless of cursor existence. 3. Row position character pattern correspond to CG RAM data bits 0 to 4 are shown above. 4. CG RAM character patterns are selected when character code bits 2 to 7 are all "0" and these are addressed by character code bits "0" and "1". 5. "1" for CG RAM data corresponds to display on and "0" to display off.
NJU6475B
(1-6) Icon display RAM (MK RAM) The NJU6475B can display maximum 128 Icons. The Icon display can be controlled by writing the data into MK RAM corresponding to the Icons. The relation between MK RAM address and Icon display position is shown in Table-4.

Correspondence among Icon Position, MK RAM Address and Data
MK RAM Address (60H - 7FH) 0110 0000 60H 0110 0001 61H 0110 0110 0110 0110 0110 0110 0110 0110 0111 0111 0111 0111 0111 0111 0111 0101 0110 0111 1000 1001 1101 1110 1111 0000 0001 0101 0110 0111 1000 1001 65H 66H 67H 68H 69H 6DH 6EH 6FH 70H 71H 75H 76H 77H 78H 79H Bits for Icon Position MK RAM Address and Data D7 D6 D5 D4 D3 D2 D1 D0 * * * 1 2 3 4 97 * * * 5 6 7 8 98 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 21 * * 25 29 45 * * 49 53 69 * * 73 77 22 * * 26 30 46 * * 50 54 70 * * 74 78 23 * * 27 31 47 * * 51 55 71 * * 75 79 24 * * 28 32 48 * * 52 56 72 * * 76 80 102 103 104 105 106 110 111 112 113 114 118 119 120 121 122
COMM1 Line and Both besides of 1st Line (COM1,COM3,COM5,COM7)
COMM2 Line and Both besides of 2nd Line (COM9,COM11,COM13,COM15)
COMM3 Line and Both besides of 3rd Line (COM17,COM19,COM21,COM23)
COMM4 Line and
Both besides of 4th Line 0111 1101 7DH * * * 93 94 95 96 126 0111 1110 7EH * * * * * * * 127 (COM25,COM27,COM29,COM31) 0111 1111 7FH * * * * * * * 128 Notes : 1. When the Icon display function using, the system should be initialized by the software initialization Because the MK RAM is not initialized by the power on reset and hardware. 2. The cross-points between segments (SEGM1 and SEGM2) and commons (COMM1 to COMM4 and COM2 to COM32) are always set "OFF" level. 3. In the table 4, * mark are invalid, therefore both of "0" or "1" can be written but these are no meaning.
NJU6475B
(1-7) Timing generator The timing generator generates a timing signals for the DD RAM, CG RAM and MK RAM and other internal circuits. RAM and timing for the display and internal operation timing for MPU access are separately generated, so that may not interfere with each other. Therefore, when the data write to the DD RAM for example, there will be undesirable influence, such as flickering, in areas other than display area. (1-8) LCD Driver LCD Driver consists of 37-common driver and 63-segment driver. The character pattern data are latched to the addressed segment-register respectively. This latched data controls display driver to output LCD driving waveform. (1-9) Cursor Blinking control circuit This circuit controls cursor On / Off and cursor position character blinking. The cursor or blinking appear in the digit locating at the DD RAM address set in the address counter (AC). When the address counter is (08)H, a cursor position is shown as bellow.
AC6 AC 0
AC5 0
AC4 0
AC3 1
AC2 0
AC1 0
AC0 0
4-Line Display 1 1st Line 2nd Line 3rd Line 4th Line 00 10 20 30 2 01 11 21 31 3 02 12 22 32 4 03 13 23 33 5 04 14 24 34 6 05 15 25 35 7 06 16 26 36 8 07 17 27 37 9 08 18 28 38 10 09 19 29 39 11 0A 1A 2A 3A 12 0B 1B 2B 3B Display position DD RAM Address (Hexadecimal)
Cursor position Note : The cursor or blinking also appear when the address counter (AC) selects the CG RAM or the MK RAM. But the displayed cursor and blinking are meaningless. If the AC stores the CG or MK RAM address data, the cursor and blinking are displayed in the meaningless position.
NJU6475B
(2) Power on Initialization by internal circuits (2-1) Internal Reset circuits Initialization The NJU6475B is automatically initialized by internal power on initialization circuits when the power is turned on. In the internal power on initialization, following instructions are executed. During the Internal power on initialization, the busy flag (BF) is "1" and this status is kept during 6ms (fOSC=180KHz) after VDD rose to 2.4V. Initialization sequence Set Function PD=1 : Power down OFF
Contrast Control
Set (00)H to the contrast register
Display ON/OFF Control
D=0 C=0 B=0 I/D=1 S=0
: Display OFF : Cursor OFF : Cursor Blink OFF : Increment by 1 : Non shift
Set Mode Entry
Clear Display
END
Note : If the condition of power supply rise time described in the Electrical Characteristics is not satisfied, the internal Power On Initialization will not performed. In this case, the software initialization by MPU is required.
(2-2) Hardware Initialization The NJU6475B prepares RESET terminal to initialize the all system. When the "L" level is input over 1.2ms to the RESET terminal, reset sequence is executed. In this time, the busy signal is output during 6ms (fOSC=180KHz) after RESET terminal went to "H". -Timing Chart Over 1.2ms External Reset Signal 6ms
BUSY
NJU6475B
(3) Instruction The NJU6475B incorporates two registers, an Instruction Register (IR) and a Data Register (DR). These two registers store control information temporarily to allow interface between NJU6475B and MPU or peripheral IC operating different cycles. The operation of NJU6475B is determined by this control signal from MPU. The control information includes resister selection signals (RS), Read / Write signals (R/W) and data signal (SIO). shows each instruction and its operating time C RS 0 0 0 0 0 0 0 0 o 0 0 d 0 0 e 0 0 0 0 0 0 0 1 Execute Time (MAX) (fCP or fOSC =180kHz) 5.42ms
Instruction Maker Test Clear Display Return Home 0 0 0
Description All "0" code is using for maker testing. Clears Display and sets RAM address (00)H in AC. Sets RAM address (00)H in AC and returns shifted display to original position. RAM contents are not changed sets cursor move direction and display shift operation which are performed at data read/write.
R/W DB7 DB 6 DB 5 DB 4 DB3 DB2 DB1 DB0
0
0
0
0
0
1
*
83.4us
Entry Mode Set 0 0 0 0 0 0 0 1 I/D S
0us
Display ON/OFF Control
0
0
0
0
0
0
1
D
C
B
Cursor or Display Shift Function Set
0 0
0 0
0 0
0 0
0 1
1 S/C R/L * * *
* *
* PD
Set Display Control On /Off (D), cursor On /Off (C) 0us and character blinking (B) at cursor position. moves cursor and shifts disCursor : play without changing RAM(DR) 83.4us contents. Display : 0us Sets Interface data length (DL) and power down mode (PD). 0us
Electronic Volume Register Set RAM Address Set
0 0
0 0
0 1
1
*
*
Electronic volume Address
Sets Vreg data to EVR control register. Sets RAM Address. After this instruction, the data is transferred to/from RAM. When LCD/Key= "1", reads key data out. Writes data into DD or CG or MK RAM. DD RAM : Display data RAM CG RAM : Character generator RAM MK RAM : Icon display RAM AC : Address counter use for DD, CG and MK RAM
0us 83.4us
Key Data Read Data Write to CG or DD or MK RAM
0
1
Read Data (KEY DATA)
0us 83.4us When FRQ is changed, the execute time is also changed.
* : Don't care
Write Data (DD RAM) (CG RAM) * * * (MK RAM) I/D=1:Increment, I/D=0:Decrement, S=1:Include Display Shift, S/C=1:Shift Display, S/C=0:Cursor shift, R/L=1:Shift to Right, R/L=1:Shift left, PD=0:Power Down Mode PD=1:Cancel Power Down Mode 1 0
Note : If the oscillation frequency is changed, the execution time is also changed.
NJU6475B
(3-1) Description of each instructions (a) Maker Test RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
Code (b) Clear Display
Code
RS 0
R/W 0
DB7 0
DB6 0
DB5 0
DB4 0
DB3 0
DB2 0
DB1 0
DB0 1
Clear Display Instruction is executed when the code "1" is written into DB0. When this instruction is executed, the space code (20)H is written into every DD RAM address, then the DD RAM (00)H is set into address counter and I/D of entry mode is set as increment mode. If the cursor or blink are displayed, they are returned to the left end of the 1st line on the LCD panel. In addition, S of entry mode is not changes and contents of MK RAM and CG RAM are also not changed. Note : The character code (20)H must be blank code in the user defined character pattern (Custom font).
(c) Return Home Code RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 * *= Don't Care
Return Home instruction is executed when the code "1" is written into DB1. When this instruction is executed, the DD RAM address (00)H is set into the address counter. Display is returned to its original position if shifted, the cursor or blink are returned to the left end of the 1st line on the LCD if the cursor or blink are operating. The DD RAM contents do not change. (d) Entry Mode Set RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 I/D DB0 S
Code
Entry Mode Set instruction which sets the cursor moving direction and display shift On/Off, is executed when the code "1" is written into DB2 and codes of (I/D) and (S) are written into DB1 (I/D) and DB0 (S). (I/D) sets the address increment or decrement, and the (S) sets the entire display shift at the DD RAM writing. I/D 1 0 S Function Address increment : The address of the DD RAM or CG RAM increment (+1) when the read/write operation, and the cursor or blink moves to the right. Address decrement : The address of the DD RAM or CG RAM decrement (-1) when the read/write operation, and the cursor or blink moves to the left. Function Entire display shift. The shift direction is determined by I/D. : shift to left at I/D=1 and shift to the right at the I/D=0. The shift is operated only for the character, so that it looks as if the cursor stands still and display moves. The display does not shift when reading from DD RAM and writing/reading into/from CG RAM. The display does not shift.
1
0
NJU6475B
(e) Display ON/OFF Control Code RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0 B
Display ON/OFF control instruction which controls the whole display ON/OFF, the cursor ON/OFF and the cursor position character blink, is executed when the code "1" is written into DB3 and codes of (D), (C) and (B) are written into DB2 (D), DB1 (C) and DB0 (B), as shown below. D 1 0 Function Display On Display Off. In this mode, the display data remains in the DD RAM so that it is retrieved immediately on the display when the D changes to 1. Function Cursor On. The cursor is displayed by 5 dots on the 8th line. Cursor Off. Even if the display data write, the I/D etc does not change. Function The cursor position character is blinking. Blinking rate is 480ms at fOSC=180KHz. The cursor and the blink can be displayed simultaneously. The character does not blink.
C 1 0 B 1 0
Character Font 5x7 Dots (1) Cursor Display Example (f) Cursor Display Shift Code RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1
Alternating Display (2) Brink Display Example
DB3 S/C
DB2 R/L
DB1 *
DB0 *
*= Don't Care
The cursor /display shift instruction shifts the cursor display to the right or left without writing or reading display data. This function is used to correct or search the display. The cursor moves to the 2nd line after the 12nd digit of the 1st line. Notice that 1st to 3rd line displays shift at the same time. When the displayed data are shifted repeatedly, each display moves in only same line. The 2nd and 3rd line display do not shift into the 1st and 2nd line. The contents of address counter (AC) does not change by operation of only the display shift. This instruction is executed when the code "1" is written into DB4 and the codes of (S/C) and (R/L) are written into DB3 (S/C) and DB2 (R/L), as shown below. S/C 0 0 1 1 R/L 0 1 0 1 Function Shift the cursor position to the left ((AC) is decremented by 1). Shift the cursor position to the right ((AC) is incremented by 1). Shifts the entire display to the left and the cursor follows it. shifts the entire display to the right and the cursor follows it.
NJU6475B
(g) Function Set RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 * DB3 * DB2 * DB1 * DB0 PD
Code
*= Don't Care
Function set instruction which sets the interface data length and power down is executed, when the code "1" is written into DB5 and (PD) is written into DB0, as shown below. When the power down mode is set, the display turns off automatically. Afterward, when the power down mode is reset, the display is off continuously. The display appears by the display on instruction. PD 1 0 Function Power down mode off (Normal operation) Power down mode on (the display goes to off automatically.)
(h) Set Electronic Volume Register RS 0 R/W 0 DB7 0 DB6 DB5 DB4 1 * * Higher order bit DB3 C3 DB2 DB1 DB0 C2 C1 C0 Lower order bit
Code
*= Don't Care
Contrast Control instruction which adjusts the contrast of LCD, is executed when the code "1" is written into DB6 and the codes of C0 to C3 are written into DB0 to DB3 as shown below. The contrast of LCD can be adjusted one of 16 voltage stage by setting 4 bit register. Set the binary code "0000" when contrast control unused.
C3 0
C2 0 : :
C1 0
C0 0
VLCD low
VLCD = VDD - V5
1
1
1
1
high
NJU6475B
(i) Set RAM Address RS 0 R/W 0 DB7 1 DB6 DB5 DB4 A A A Higher order bit DB3 A DB2 DB1 DB0 A A A Lower order bit
Code
The RAM address set instruction is executed when the code "1" is written into DB7 and the address is written into DB6 to DB0 as shown above. The address data (DB6 to DB0) is written into the address counter (AC) by this instruction. After this instruction execution, the data writing/reading is performed into/from the addressed RAM. The RAM includes DD RAM, CG RAM and MK RAM and these RAMs are shared by addressed as shown below. RAM Address DD RAM DD RAM DD RAM DD RAM CG RAM MK RAM (j) Write Data to CG, DD or MK RAM -Write Data to DD RAM RS 1 R/W 0 DB7 D DB6 DB5 DB4 D D D Higher order bit DB3 D DB2 DB1 DB0 D D D Lower order bit 1st Line 2nd Line 3rd Line 4th Line 4 Characters 128 Icons : : : : : : (00)H (10)H (20)H (30)H (40)H (60)H to to to to to to (0B)H (1B)H (2B)H (3B)H (5F)H (7F)H
Code
-Write Data to CG or MK RAM RS 1 R/W 0 DB7 * DB6 DB5 DB4 * * D Higher order bit DB3 D DB2 DB1 DB0 D D D Lower order bit
Code
*= Don't Care
Write Data to RAM instruction is executed when the code "1" is written into (RS) and code "0" is written into (R/W). By the execution of this instruction, the data is written into RAM. The selection of RAM is determined by the previous instruction. After this instruction execution, the address increment (+1) or decrement (-1) is performed automatically according to the entry mode set.
NJU6475B
(3-2) Initialization using the internal reset circuit When internal reset operates for initialization, the function set, Display ON/OFF Control and Entry Set instruction must be executed before the data input as shown below. Initialized No display appears
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Power On
Function Set
0
0
0
0
1
*
*
*
*
1
Power down mode OFF Turn on display and cursor. Entire display is in space mode. In case of mark display function, the contens of MK RAM should be initialized by instruction before the display on.
Display ON/OFF Control
0
0
0
0
0
0
1
1
1
0
Entry Mode Set
0
0
0
0
0
0
0
1
1
Example for address incre0 ent and cursor right shift when the data is written to the DD, CG or MK RAM.
Write data to the DD, CG or MK RAM and set the instruction
NJU6475B
(3-3) Initialization by instruction If the power supply conditions for the correct operation of the internal reset circuits are not met, the NJU6475B must be initialized by instruction.
Power On
Initialized No display appears
Wait more than 6ms after VDD rises to 2.4 V
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Function Set
0
0
0
0
1
*
*
*
*
*
Wait more than 3.0ms
Function Set
0
0
0
0
1
*
*
*
*
*
Wait more than 200us
Function Set
0
0
0
0
1
*
*
*
*
*
Function Set
0
0
0
0
1
*
*
*
*
*
Set operation and power down mode OFF.
Display Off
0
0
0
0
1
*
*
*
*
*
Display Clear
0
0
0
0
1
*
*
*
*
* Example for address increment and cursor right shift when the data is written to The DD, CG or MK RAM.
Entry Mode Set
0
0
0
0
1
*
*
*
*
*
Write data to the DD, CG or MK RAM and set the Instructions
Note : When the Icon display function using, the contents of MK RAM should be initialized by instruction before the display on.
NJU6475B
(4) Power down Function NJU6475B incorporates the power down mode to reduce the operating current. The power down mode is set/reset by the function set instruction. In the power down mode, all the character display and Icon display turn off and only static display operation is available. The status of internal circuits at the power down mode is shown below. -Main oscillator stops and sub oscillator for the static display starts the operation. -Voltage converter, Key Scan, Voltage Regulator, Voltage follower (OP-AMP) are stopped. -The contents of DD, CG, MK RAM are kept. (5) LCD Display (5-1) Power Supply for LCD Driving NJU6475B incorporates voltage converter to generate the LCD driving voltage which is adjusted by the voltage regulater and the EVR. (a) Voltage Converter -Voltage Tripler By connecting capacitor between C1+ and C1-, C2+ and C2-, VSS and V5OUT respectively, two times negative voltage of VDD--VSS output from V5OUT. -Voltage Doubler By connecting capacitor between C2+ and C2-, VSS and V5OUT respectively, and connecting the C1+ terminal to C2+ terminal, and C1- terminal being open, negative voltage of VDD--VSS output from V5OUT. VDD VSS =+3V =0V VDD VSS =+3V =0V
V5OUT = -3V Voltage Doubler V5OUT = -6V
Voltage Tripler (b) Voltage Regulator Voltage Regulator incorporates a OP-AMP which is supplied VDD and V5OUT, and a reference voltage source (VREF). By setting the VR level by connecting Ra and Rb, the regulator which amplifies VREF, outputs the LCD driving voltage to the VREG terminal. Therefore the LCD driving voltage can be output between VDD and VREG by setting. VREG = ( 1+ Rb / Ra) VREF in condition, VDD = 0V, VREG < V5OUT
The EVR functions VREF value adjustment from 1st step to 16th by a step when the 4 bit data write into the EVR register by the instruction. Set the EVR register to (00)H when the EVR function is unused. Use variable resistances to external to the external resistances Ra, Rb and thermistor if need due to the voltage reference VREF is changed by the lot and operating temperature. Take care the noise input on the VR terminal because of it is designed with high impedance. Short wiring should be required to avoid the noise input, if necessary.
NJU6475B
[ The Voltage Reference VREF Characteristics ]
Supply Voltage
:
VDD = 0V, VSS = -3V
Temperature : 25 C
-5
VREG(V)
-6
-7
-8 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH0DH 0EH 0FH
Electric Volume value
[ The LCD Operating Voltage VREG Characteristics ]
Supply Voltage : VDD = 0V, VSS = -3V, External Resistances : Ra = 180K, Rb = 820K Used Formulation
Voltage Tripler Output : V5OUT = -9V Temperature : 25 C
: VREG(XX)H = (1 + 820k/180k) VREF(XX)H
-1.05 -1.1 VREF(V) -1.15 -1.2 -1.25 -1.3
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH
Electric Volume value
NJU6475B
(c) Bleeder Resistance Each LCD driving voltage (V1, V2, V3, V4, V5) is generated by the high impedance bleeder resistance buffered by voltage follower OP-AMP to get a enough display characteristics with low operating current. The bleeder resistance is set 1/7 bias suitable for 1/36 duty by 5M resistance in total. The capacitor connected between V5 and VDD is needed for stabilizing V5. The determination of the each capacitance of C1, C2 and C3 generating for LCD operating voltage is required to operate with the LCD panel actually. The capacitance for the typical application is shown below: LCD Driving Voltage vs Duty Power Supply VLCD Duty Ratio Bias 1/36 1/7 VDD - V5
VLCD is the maximum amplitude for LCD driving voltage.
Typical application for LCD operating voltage generation Note : Take care the noise into the VR terminal as designed with high impedance. Short wiring or sealed wiring are required to avoid the noise, if necessary.
NJU6475B
(5-2) Relation between oscillation frequency and LCD frame frequency As the NJU6475B incorporates oscillation capacitor and resistor for CR oscillation, 180KHz oscillation is available without any external components. (1 Clock = 5.56us)
1/36 Duty
1 frame = 5.56 (us) x 62 x 36 = 12.4 (ms) Frame frequency = 1 / 12.4 (ms) = 80.6 (Hz)
NJU6475B
(6) Key Scan Circuit (6-1) Key scan timing chart CHATTERING K0 to K3 Continuously 3 times "L" detection Continuously 3 times "H" detection KEYCHECK (Inner Side H H H L L L KEYCHECK 0.71mS KEYCHECK L H H L H H H KEYCHECK of NJU6475B) Fig. 1 REQ Fig. 2 LCD/KEY R/W DB7/CS LCD DATA(Write) E/SCL Set Key Register (Inner Side of NJU6475B) S0 to S7 Fig. 4 (6-2) Key Scan 1. KEYCHECK signal always operates to check the status of keys excepting for power down mode. 2. When Key signal (K0 to K3) 3 times detected continuously at rise up edge of KEYCHECK (inner side NJU6475), key Scan circuit performs output request signal (REQ terminal) rise to "H" and simultaneously key input information transmit to CPU. Its useful for anti-chattering. At the same time of REQ signal output, the key register status is "00010000 00000000" (Non Key Input) automatically. Key input terminal (K0 to K3) are "H" in normal, then turn to "L" when Key input. CHATTERING K0 to K3 Continuously 3 times "L" detection KEYCHECK (Inner Side HHHLLL 0.71mS of NJU6475B) REQ Fig. 1 Fig. 3 CHATTERING
Set "00010000 00000000" into Register "Hi-Z"
In case of request signal "H", When detects 3 times continuously key released status, request signal will be "L". CHATTERING K0 to K3 Continuously 3 times "H" detection KEYCHECK (Inner Side LHHLHHH of NJU6475B) REQ Fig. 2
NJU6475B
3. When the request signal is detected, CPU should be LCD / KEY to "H" and read out key data by instruction. 16-bit key data synchronizing to "SCL" (SCL terminal) is read out to CPU. (1st time output key data was fixed as "00010000 00000000") keyscan operation start from the next rising edge of SCL after the end of key data read out opration.
Fig. 3
4. The key data are gotten from 4 terminals (K0 to K3) at each timing of key scan signals (S0 to S7). The detected data are up dating anytime and stores to key register.
S0 "L" S1 * * * S7 0.45mS Fig. 4 End of Key Scan
- Key scan timing : 0.45ms (fosc = 180KHz,MAX =0.64ms) - Pulth width : 45us (fosc = 180KHz, MAX =64us)
NJU6475B
(6-3) Key scanning timing Key status is gotten at 3/4 port timing of tkp during "L" period of S0 to S7.
S0 tkp S1 1/4 tkp 3/4 tkp * * * * *
Detecting timing
(6-4) The format of detection 1st Byte MSB 0 0 0 1 KL3 KL2
LSB KL1 KL0
2nd Byte MSB KH7 KH6
LSB KH5 KH4 KH3 KH2 KH1 KH0
Fix KL3 to KL0 : Corresponds to K3 to K0
KH7 to KH0 : Corresponds to S7 to S0
( For Example )
1st Byte MSB 0 0
0
1
1
1
0
LSB 0
2nd Byte MSB 0 0
0
0
0
1
0
LSB 0
NJU6475B
(6-5) Key roll over input NJU6475B can be accepted the key roll over input. In case of key roll over input, the output results are shown below; -Connecting same SX signal line at multiple key push.
When key-in shown above case, the data contents are "00011100" "00000100".
-The case of connecting different SX signal line at multiple key push (1)
When key-in shown above case, the data contents are "00010100" "00010100".
NJU6475B
-The case of connecting different SX signal line at multiple key push (2)
When key-in like as shown above, the data contents are "00010101" "00010100". In this case, the result will be same, at each key-in shown below. [Case 1] [Case 2]
[Case 3]
[Case 4]
[Case 5]
[Case 6]
NJU6475B
(6-6) The inner composition of Key Scan circuit The inner composition of key scan circuit shown below :
N J U 6 4 7 5 B Inner Circuit
***
Output Nch O Open drain
O
O
O
Input Pull up schmitt
S0
S1
S7
K0
K1
K2
K3
* * *
-In case of non input the key each terminal status shown below: S0 to S7 : The status of Nch FET output side is ON, output result is "L". K0 to K3 : The status is "H" by pull-up resistance. -When any key key-in, KX of key-in side turn to "L" and it can confirms. -Input terminal (K0 to K3) are composed by schmitt inverter input method.
NJU6475B
(7) Interface with MPU Interface circuit of NJU6475B can be connected to serial by turn to "L" P/S terminal on shown below serial data timing. And DB0 to DB5 can be use to output port.
Notes : RS, R/W, LCD/KEY requires setting before CS fall down. RS is unrelated to read out of key data and writing of port data. Serial interface circuit is in operation at CS is "L". When SCL rises, input data was lead, and rises CS case loading input data. When the input data was less than 16 bits, input data will be invalid at rises CS. And so on equal or over than 16 bits case, rear side total 16 bits are effectiveness. The input data should be total 16 bits. The data of read/write are composed MSB first.
NJU6475B
-Data format
The data formatted by 2 byte form at read/write. When writing data consists LCD data and port data. The using data in write mode means one of key data. In write mode of data format, 1st byte means recognition data of LCD data and Port data. In "0110 0000" (fixed) selects LCD data, in "0110 0001" (fixed) selects Port data. The data of 2nd byte consists each data contents. When the 1st byte of MSB 4 bit data are not "0110", in this case the input data will be invalid.
*
D7
D6
D5
D4
D3
D2
D1
D0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
*
LCD/ KEY
RS
R/W
1st Byte Higher Selected Bit (0110) Lower Selected Bit (0000)
2nd Byte
LCD Data
0
0
0
LCD Data (Instruction)
Instruction Execution Time
LCD Data
0
1
0
Higher Selected Bit (0110)
Lower Selected Bit (0000)
LCD Data (RAM Data)
Instruction Execution Time
PORT Data
0
*
0
Higher Selected Bit (0110)
Lower Selected Bit (0001)
Output Port (Set "L"=0,"H"=1) Instruction Execution Time DB5 DB4 DB3 DB2 DB1 DB0
*
*
Key Data 1
KEY Data
Key Data 2 KL0 KH7 KH6 KH5 KH4 KH3 KH2 KH1 KH0
1
*
1
Selected Bit (0001)
KL3
KL2
KL1
* : Invalid Data Notes : The instruction requires execution time after transmit 16 bit data. After transmit data can not transmit continuously
NJU6475B
MAXIMUM ABSOLUTE RATINGS
PARAMETER Supply Voltage (1) Input Voltage Operating Temperature Storage Temperature
SYMBOL VDD Vt Topr Tstg
RATINGS - 0.3 ~ + 7.0 - 0.3 ~ VDD + 0.3 - 30 ~ + 80 - 55 ~ + 125
UNIT V V C C
NOTE
Note-1 : If the LSI are used on condition above the absolute maximum ratings, the LSI may be destroyed. Using the LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the electric characteristics conditions will cause malfunction and poor reliability. Note-2 : Decoupling capacitor should be connected between VDD and VSS due to the stabilized operation for the voltage converter. Note-3 : All voltage value are specified as VSS = 0V. The relation : VDD > VSS, VDD > VSS V5out, VSS = 0V must be maintained.
NJU6475B
ELECTRICAL CHARACTERISTICS (VDD = 2.4 ~ 3.6V, Ta = -20 ~ +75 C) PARAMETER Input Voltage 1 Input Voltage 2 Input Voltage 3 Output Voltage 1 Output Voltage (S0 ~ S7) Driver ON-resist (COM) Driver ON-resist (SEG) Driver Output-resist (COM) Driver Output-resist (SEG) Driver current Input Leak Current Pull-up MOS Current
SYMBOL
CONDITIONS
(OSC1, Except terminals K0 ~ K3) (OSC1, Except terminals K0 ~ K3)
(Application to terminals K0 ~ K3) (Application to terminals K0 ~ K3)
VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH1 VOL1 VOL2 RCOM1 RSEG1 RCOM2 RSEG2 IV1 IV4 ILI -Ip IDD1 IDD2 V5OUT Vef V1 V2 V3 V4
(Applicate to terminal OSC1) (Applicate to terminal OSC1) -IOH = 0.205mA, VDD = 3.0V IOL = 1.6mA, VDD = 3.0V IOL = 300uA Id = 1uA (All COM Terminal) VO = VDD, V5 Id = 1uA (All SEG Terminal) VO = VDD, V5 Id = 1uA (All COM Terminal) VO = V1, V4 Id = 1uA (All SEG Terminal) VO = V2, V3 V1 Sink Current V4 Source Current Vin = 0 ~ VDD
VDD = 3V (ALL DB, K0 ~ K3 terminal)
MIN. 0.8VDD VSS 0.8VDD VSS VDD-0.5 VSS 2.0 16.8 -1 10
TYP. 25 320 -
MAX. VDD 0.2VDD VDD 0.2VDD VDD 0.5 0.5 0.6 20 30 40 50 -12.3 1 50 380 640
UNIT
NOTE
V V V V V V V V V k k k k uA uA uA uA uA uA V %
4 4 4 4 4 4 5 5 8 8 8 8
6 7 7
Operating Current voltage converter Part Output Voltage Voltage Efficiency
fOSC = Internal OSC on Display VDD = 3V, On display, V5 = -5V fOSC = Internal OSC on Display VDD = 3V,On access, tCYCE = 5uS
VDD = 3V Ta = 25C RL =
IOUT 3 Times = 100uA 3 Times
-4.6 90.0 2.44 2.01 0.73 0.30
-4.8 95.0 2.57 2.14 0.86 0.43 2.70 2.27 0.99 0.56
LCD Drive Voltage
Ta = 25C VDD = 3V V5 = 0V Measured at COM/SEG terminal VDD - V5 = 3V
V
Bleeder Resistance RB(VDD - V5)/IB
IB:Bleeder Resistance Cur.
RB
5.0
M
RB : 5 Bleeder Resist Output Voltage reg. Operating voltage Reference Voltage Clock Oscillation Freq. LCD Driving Voltage
VREG V5OUT VREF fOSC VLCD
, RRV=1M, V5OUT = -10.8V VDD Reference VDD Reference, Ta=25C VDD = 3V, Ta=25C V5OUT Terminal, VDD = 3V
RL =
VDD-10.8 VDD-11 VDD-0.75 125 VDD-3
VDD-1.05 180 -
VDD-1.8 VDD-3.6 VDD-1.35 235 VDD-13.5
V kHz V
9
NJU6475B
Note-4 : Input/Output structure except LCD display are as shown below. -Input terminal structure (without pull-up MOS) Applicated terminals : E/SCL, RS, R/W, P/S, SEL, RESET, LCD/KEY
(Pull-up with MOS, schmitt) K0 ~ K3
(Pull down MOS) TEST
-Input terminals structure Applicated terminal : OSC1
-Common terminals Input/Output structure. Applicated terminal : DB7 to DB0
NJU6475B
Note-5 : Apply to the output and Input/Output Terminals. Note-6 : Except current of pull-up MOS and output drive MOS. Note-7 : Except Input/Output part current but including the current on bleeder resistance. If the input level is medium, current consumption will increase due to penetration current. therefore, the input level must be fixed to "H" or "L".
-Operating Current Measurement Circuit
Note-8 : Rcom and Rseg are the resistance values between power supply terminals (VDD, V5OUT) and each common terminal (Com1 to Com32 / COMM1 to COMM4) and Supply voltage (VDD, V5OUT) and each segment terminal (SEG1 to SEG60 / SEGM1 to SEGM2) respectively, and measured when the current Id is flown on every common and segment terminals at same time. Note-9 : Apply to the voltage from each COM and SEG are less than 0.15V against the LCD driving contrast voltage (VDD, V5OUT) at no load condition.
NJU6475B
BUS TIMING CHARACTERISTICS -Serial Interface sequence (VDD = 2.4 ~ 3.6V, VSS = 0V, Ta = -20 ~ +75C) PARAMETER Serial clock cycle time Serial clock "High" level width "Low" level Serial clock rise and fall down time Chip select pulse width Chip select set up time Chip select hold time Chip select rise and fall time Set up time RS, R/W, LCD/KEY-CS Address hold time Serial input data set up time Serial input data hold time Serial output data delay time Serial output data hold time SYMBOL tCYCE tSCH tSCL tSCr, tSCf PWCS tCSU tCH tCSr, tCSf tAS tAH tSISU tSIH tSOD tSOH MIN. 1 300 700 500 200 300 200 200 200 200 200 MAX. 20 20 700 CONDITION Fig. 1 Fig. 1 Fig. 1 Fig. 1 Fig. 1 Fig. 1 Fig. 1 Fig. 1 Fig. 1 Fig. 1 Fig. 1 Fig. 1 Fig. 1 Fig. 1 UNIT uS nS nS nS nS nS nS nS nS nS nS nS nS nS
Serial Interface
Fig. 3 Serial Interface Sequence Characteristics
NJU6475B
-I/O Part sequence PARAMETER Port set time SYMBOL tPS MIN. MAX. 500 CONDITON Fig. 2 UNIT uS
-The load of DB0 to DB7 is CL = 100 pF
CS VIH1 VIH1 DB0 ~ DB5 tPS VIL1
Fig. 2 I/O Port Sequence (Serial Interface) -The input conditions of using hardware reset circuit. Input Timing tRSL RESET
VIL PARAMETER Reset Input RAW level width SYMBOL tRSL CONDITION MIN. 1.2 TYP. MAX. UNIT ms
-The power supply conditions of using power on reset circuit.
(Ta = -20 ~ +75C) PARAMETER The power supply rise time The power OFF time SYMBOL trDD tOFF CONDITION MIN. 0.1 1 TYP. MAX. 5 UNIT ms ms
Since the internal initialization circuits will not operate normally unless the above conditions are met, in such a case of initialized by instruction. (Refer to initialization by the instruction) tOFF specifies the power off time in a short period off or cyclical on/off.
* tOFF specifies the power off time in a short period off or cyclical ON/OFF.
NJU6475B
-Key Scan Sequence
PARAMETER E/SCL-S0 to S7 Delay time Key scan pulse width "H","L" level Key scan time REQ output delay time Key in check signal frequency -The load of K0 to K3 is CL = 20 pF SYMBOL tKDS tKP tKS tKDR tKF MIN. 0.98 TYP. 66.7 44.4 0.36 1.41 MAX. 300 48 0.38 1.0 1.84 CONDITION Fig. 3 Fig. 3 Fig. 3 Fig. 3 Fig. 3 UNIT uS uS mS uS KHz
0.7VDD KEYCHECK 0.5VDD 1 / tKF 0.5VDD
0.7VDD
0.7VDD REQ tKDR 0.3VDD tKDR
SCL/E
VIH1 tKDS
S0
S1
S2
S3
S4
S5 tKP S6
S7 tKS
Fig. 3 Key scan sequence
NJU6475B
-External clock input PARAMETER External clock operating frequency External clock duty External clock rise time External clock fall time SYMBOL fCP Duty tCPr tCPf MIN. 125 45 MAX. 235 55 0.2 0.2 CONDITION Fig. 4 Fig. 4 Fig. 4 Fig. 4 UNIT KHz % uS uS
TfCP TK TI Duty = TK + TI OSC1 VDD-0.5 0.5VDD VDD+0.5 tCPf Fig.4 External clock input tCPr TfCP = 1/fCP TK
-The key scan circuit timing characteristics measurement cricurit
NJU6475B S0(S1~7) K0(K1~3)
CL=20pF
NOTE : SW Resistance is 0 (measurement : only pattern wires)
NJU6475B
LCD DRIVING WAVE FORM
NJU6475B
APPLICATION CIRCUIT (1)
12-Character 4-Line (Terminal description, Mode A)
NJU6475B
APPLICATION CIRCUIT (2)
12-Character 4-Line (Terminal description, Mode B)
NJU6475B MEMO
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

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